1. Field of the Invention
This invention relates generally to semiconductor processing and, more particularly, to minimizing parasitic resistances in semiconductor devices.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor, e.g., channel length, junction depths, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size or scale of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Generally, a field effect transistor is comprised of a semiconductor substrate having source/drain regions formed therein. The source/drain regions may be separated by a distance roughly equivalent to the width of a gate structure formed above a surface of the semiconductor substrate. Furthermore, sidewall spacers may be formed adjacent to the gate structure and may function to electrically isolate the gate structure from the source/drain regions. Those skilled in the art will appreciate that, prior to forming the sidewall spacers, lightly doped regions may be formed in the semiconductor substrate adjacent to the gate structure. Once the transistor is formed, portions of the lightly doped regions and the source/drain regions may be positioned in the semiconductor substrate underneath the sidewall spacers. The lightly doped regions and the source/drain regions together may form the familiar lightly doped drain (LDD) structure.
Those skilled in the art will appreciate that, during normal operation, the gate structure and the source/drain regions may be coupled to various inputs and supply voltages. Moreover, during normal operation, a transistor drive current may be determined by, among other things, the resistance between the source/drain regions, which is typically referred to as R.sub.on. As a general rule, the drive current of a transistor may be increased by decreasing R.sub.on, and conversely, the drive current of a transistor may be decreased by increasing R.sub.on (i.e., transistor drive current varies inversely with R.sub.on.) Furthermore, the operating speed of the transistor may vary directly with drive current. As a general rule, all other things being equal, increasing the transistor drive current increases the transistor operating speed. For example, by increasing the drive current, a transistor that normally operates at 400 MHz may be made to operate at 500 MHz.
One method currently used to decrease R.sub.on and, thus, improve the operating speed of field effect transistors, is salicide-processing of the source/drain regions. For example, a thin metal film may be deposited above the surface of the source/drain regions. Once deposited, the transistor may be exposed to a heating process, which may result in the diffusion of the deposited metal film into the exposed portions of the source/drain regions. Next, the non-reacted portion of the metal film may be selectively removed (i.e., the non-diffused portion of the metal film is removed), and the transistor may be exposed to a second heating process resulting in the formation of silicide in and above the source/drain regions. This process tends to make the source/drain regions more conductive.
A significant contributor to R.sub.on is high parasitic resistance caused by the poor conductivity of the LDD-layers underneath the sidewall spacers. Unfortunately, the LDD-layers positioned underneath the sidewall spacers are unaffected by conventional salicide-processing. Consequently, the parasitic resistance associated with the LDD-layers positioned under the sidewall spacers may not be reduced using conventional salicide-processing. Furthermore, conventional salicide-processing requires multiple processing steps, which may increase manufacturing complexity and cost.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.